The present invention relates to a semiconductor device, more specifically a semiconductor device having narrow pitches of interconnections, etc.
As the information society is advanced, the semiconductor devices are required to be further micronized and to be higher integrated.
In semiconductor devices, such as SRAMs, FLASH memories, etc., the interconnections and the conductor plugs are arranged in extremely high densities in the memory cell region. The interconnections, the conductor plugs, etc. are arranged in extremely high densities, whereby the memory cells can have the sizes reduced, and resultantly the memory capacities can be increased.
Following references disclose the background art of the present invention.
[Patent Reference 1]
Specification of Japanese Patent Application Unexamined Publication No. 2003-174105
[Patent Reference 2]
Specification of Japanese Patent Application Unexamined Publication No. 2003-258090
[Patent Reference 3]
Specification Of Japanese Patent Application Unexamined Publication No. 2003-124249
[Patent Reference 4]
Specification of Japanese Patent Application Unexamined Publication No. 2002-76048
However, interconnections and conductor plugs which are arranged in extremely high densities tend to easily short circuit with each other. The short circuits with adjacent interconnections and conductor plugs lead to lower fabrication yields of semiconductor devices. FIG. 31 is a plan view of adjacent interconnections which are short circuited with each other. As illustrated in FIG. 31, the interconnections 164 are arranged at an extremely narrow pitch. As indicated by the dot-line circle, conductor plugs 162 are buried below the interconnections 164, formed integral with the interconnections 164. The interconnections 164 and the conductor plugs 162 are buried in an insulation layer 152 by dual damascene. The solid line circle indicates the short circuit between the adjacent interconnections 164.
The use of ArF exposure systems and half-tone phase shift masks can allow larger margins in the exposing process, whereby the short circuit between the interconnections can be prevented, and the interconnection pitch can be small. However, the ArF exposure systems and half-tone phase shift masks are so expensive that they cannot meet the requirement of cost reduction of semiconductor devices.